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LPC213X Datasheet, PDF (1/2 Pages) NXP Semiconductors – ARM7-based microcontrollers with two 10-bit ADCs and 10-bit DAC
60-MHz, 32-bit
microcontroller with
ARM7TDMI-S™ core
LPC213x
ARM7-based microcontrollers with
two 10-bit ADCs and 10-bit DAC
These powerful yet cost-effective microcontrollers have up to 512 KB of ISP/IAP Flash and up to
32 KB of SRAM. Each has up to two 10-bit A/D converters, a 10-bit D/A converter, two I2C-bus
interfaces, and Fast I/O.
Key features
4 60-MHz, 32-bit ARM7TDMI-S with
AHB/APB interfaces
4 Up to 512 KB ISP/IAP Flash
4 Up to 32 KB SRAM
4 Very fast Flash programming via on-
chip boot loader software
4 Up to two 10-bit A/D converters (with
enhanced features on LPC213x/01
versions)
4 10-bit D/A converter
4 Multiple serial interfaces: two I2C, two
UART, one SPI, and one SSP
4 Two 32-bit timers
4 Real-time clock and Watchdog timer
4 7 Fast I/O pins (5-V tolerant) with up
to 15-MHz switching (LPC213x/01
versions only)
4 Single 3.3-V supply
4 Packages:
– LQFP64 (10 x 10 x 1.4 mm)
– HVQFN64 (9 x 9 x 0.85 mm)
Applications
4 Automotive entertainment
4 Connectivity
4 Display
4 Communications gateways and
protocol converters
4 Software modems
4 Voice recognition
4 Low-end imaging
The NXP microcontroller family LPC213x
uses a high-performance 32-bit ARM7
core that operates at up to 60 MHz.
Each device has up to 512 KB of on-chip
Flash and up to 32 KB of on-chip SRAM
memory.
In-System Programming (ISP) and In-
Application Programming (IAP) software
minimize programming time – each 256-
byte line takes only 1 ms to program,
and a single-sector or full-chip erase
takes only 400 ms.
A 128-bit-wide memory interface and
a patented memory accelerator enable
32-bit code execution from Flash with
zero wait-states. For applications where
code size is critical, an alternative 16-bit
Thumb mode reduces code by more
than 30% with minimal performance
penalties.
Each device is equipped with up to
two 10-bit A/D converters and a 10-bit
D/A converter. The A/D converters
have eight channels apiece and, on the
LPC213x/01 versions, result registers for
each channel.
Multiple serial communications
interfaces increase design flexibility,
provide larger buffer size, and deliver