LPC18S50 Datasheet, PDF (1/151 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 flashless MCU with security features

LPC18S50/S30/S10
32-bit ARM Cortex-M3 flashless MCU with security features;
up to 200 kB SRAM; Ethernet, two HS USB, LCD, EMC, AES
Rev. 1 — 23 February 2015
Product data sheet
1. General description
The LPC18S50/S30/S10 are ARM Cortex-M3 based microcontrollers with security
features for embedded applications. The ARM Cortex-M3 is a next generation core that
offers system enhancements such as low power consumption, enhanced debug features,
and a high level of support block integration.
The LPC18S50/S30/S10 operate at CPU frequencies of up to 180 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The LPC18S50/S30/S10 include up to 200 kB of on-chip SRAM, security features with
AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM
(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external
memory controller, and multiple digital and analog peripherals.
See Section 17 “References” for additional documentation.
2. Features and benefits
 Processor core
 ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.
 ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
 Non-maskable Interrupt (NMI) input.
 JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
 System tick timer.
 On-chip memory
 200 kB SRAM for code and data use.
 Multiple SRAM blocks with separate bus access.
 64 kB ROM containing boot code and on-chip software drivers.
 64 bit One-Time Programmable (OTP) memory for general-purpose use.
 Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key
storage One bank can store an encrypted key for decoding the boot image.
 AES engine for encryption and decryption of the boot image and data with DMA
support and programmable via a ROM-based API.
 Clock generation unit