LPC1100L Datasheet, PDF (1/2 Pages) NXP Semiconductors – Cortex-M0 MCUs with lowest active power and superior code density

NXP 50-MHz, 32-bit
Cortex-M0™ microcontrollers
LPC1100L
Cortex-M0 MCUs with lowest active
power and superior code density
Built around the new Cortex-M0 architecture, the smallest, lowest power, and most energy-efficient
ARM core ever developed, these MCUs are ideally equipped for use in many traditional 8/16-bit
applications.
Key features
} ARM Cortex-M0 processor
- 50 MHz operation
- N ested Vectored Interrupt Controller for fast deterministic
interrupts
- W akeup Interrupt Controller allows automatic wake from
a priority interrupt
- T hree reduced-power modes: Sleep, Deep-sleep,
and Deep power-down
} Memories
- Up to 32 KB Flash memory
- Up to 8 KB SRAM
} Serial peripherals
- U ART with fractional baud rate generation, internal FIFO,
and RS-485 support
- U p to 2 SPI controllers with FIFO and multi-protocol
capabilities
- I²C-bus interface supporting full I²C-bus specification and
Fast-mode Plus (Fm+) with a data rate of 1 Mbit/s, multiple
address recognition, and monitor mode
} Analog peripheral
- 10-bit analog-to-digital converter with eight channels and
conversion rates up to 400 K samples per second
} Other :
- Up to 42 general-purpose I/O (GPIO) pins with configurable
pull-up/down resistors and a new, configurable open-drain
operating mode
- Four general-purpose counter/timers, with a total of four
capture inputs and 13 match outputs
- Programmable watchdog timer (WDT) with lock-out feature
- System tick timer
- Each peripheral has its own clock divider for power savings
Applications
} White goods
} e-Metering
} Consumer peripherals
} Remote sensors
} 8/16-bit applications
} Industrial networking
} System supervisors