HEF4517B_09 Datasheet, PDF (1/15 Pages) NXP Semiconductors – Dual 64-bit static shift register

HEF4517B
Dual 64-bit static shift register
Rev. 06 — 10 December 2009
Product data sheet
1. General description
The HEF4517B consists of two identical, independent 64-bit static shift registers. Each
register has separate clock (nCP), data input (nD), parallel input-enable/output-enable
(nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to
nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of
the clock, regardless of the state of nPE/OE.
When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode.
When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit
shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the
clock input makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended V_DD power supply range of 3 V to 15 V referenced to V_SS
(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input. It is
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
2. Features
„ Tolerant of slow clock rise and fall times
„ Fully static operation
„ 5 V, 10 V, and 15 V parametric ratings
„ Standardized symmetrical output characteristics
„ Operates across the full industrial temperature range −40 °C to +85 °C
„ Complies with JEDEC standard JESD 13-B
3. Applications
„ Industrial
4. Ordering information
Table 1. Ordering information
All types operate from −40 °C to +85 °C
Type number
Package
Name
Description
HEF4517BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4517BT
SO16
plastic small outline package; 16 leads; body width 7.5 mm
Version
SOT38-4
SOT162-1