HEF4043B Datasheet, PDF (1/13 Pages) NXP Semiconductors – Quadruple R/S latch with 3-state outputs

HEF4043B
Quad R/S latch with 3-state outputs
Rev. 06 — 11 November 2008
Product data sheet
1. General description
The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable
input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown
in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
does not affect the state of the latch. The high impedance off-state feature allows common
bussing of the outputs.
It operates over a recommended V_DD power supply range of 3 V to 15 V referenced to V_SS
(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input. It is
also suitable for use over the industrial (−40 °C to +85 °C) temperature range.
2. Features
I Fully static operation
I 5 V, 10 V, and 15 V parametric ratings
I Standardized symmetrical output characteristics
I Operates across the full industrial temperature range −40 °C to +85 °C
I Complies with JEDEC standard JESD 13-B
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
3. Applications
I Four-bit storage with output enable
4. Ordering information
Table 1. Ordering information
All types operate from −40 °C to +85 °C.
Type number Package
Name
Description
HEF4043BP
DIP16
plastic dual in-line package; 16-leads (300 mil)
HEF4043BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1