HEF4015BT-653 Datasheet, PDF (1/15 Pages) NXP Semiconductors – Tolerant of slow clock rise and fall times

HEF4015B
Dual 4-bit static shift register
Rev. 8 — 21 November 2011
Product data sheet
1. General description
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel
converter). Each shift register has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input
(MR). Information present on D is shifted to the first register position, and all the data in
the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A
HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.
The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise
and fall times.
It operates over a recommended V_DD power supply range of 3 V to 15 V referenced to V_SS
(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.
2. Features and benefits
 Tolerant of slow clock rise and fall times
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Specified from 40 C to +85 C.
 Complies with JEDEC standard JESD 13-B
3. Applications
 Serial-to-parallel converter
 Buffer stores
 General purpose register
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name
Description
HEF4015BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4015BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1