CBTV4020 Datasheet, PDF (1/16 Pages) NXP Semiconductors – 20-bit DDR SDRAM 2 : 1 MUX

CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
Rev. 03 — 4 April 2008
Product data sheet
1. General description
This 20-bit bus switch is designed for 2.3 V to 2.7 V V_DD operation and SSTL_2 select
input levels.
Each host port pin is multiplexed to one of two DIMM port pins. When the SEL pin is HIGH
the A DIMM port is turned on and the B DIMM port is off. The ON-state connects the host
port to the DIMM port through a 20 Ω nominal series resistance. When the port is off a
high-impedance state exists between the Host and disabled DIMM. The DIMM port is
terminated with a 100 Ω resistor to ground. When the SEL pin is LOW the B DIMM port is
turned on and the A DIMM port is off.
The part incorporates a very low crosstalk design. It has a very low skew between outputs
(< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optimal
performance in DDR data bus applications.
Each switch has been optimized for connection to 1-bank or 2-bank DIMMs.
The low internal RC time constant of the switch (20 Ω × 7 pF) allows data transfer to be
made with minimal propagation delay.
The CBTV4020 is characterized for operation from 0 °C to +85 °C.
2. Features
I SEL signal is SSTL_2 compatible
I Optimized for use in Double Data Rate (DDR) SDRAM applications
I Designed to be used with 400 Mbit/s 200 MHz DDR data bus
I Switch ON resistance is designed to eliminate the need for series resistor to DDR
SDRAM
I R_ON ~ 20 Ω
I Internal 100 Ω pull-down resistors on DIMM side when path is disabled
I Low differential skew
I Matched rise/fall slew rate
I Low crosstalk
I One DIMM select control line
I Latch-up protection exceeds 500 mA per JESD78
I ESD protection exceeds 1500 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101