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BLD6G21L-50 Datasheet, PDF (1/14 Pages) NXP Semiconductors – TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor | |||
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BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty
transistor
Rev. 01 â 28 October 2009
Objective data sheet
1. Product proï¬le
1.1 General description
The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution
using NXPâs state of the art GEN6 LDMOS technology. This device is perfectly suited for
TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The
main and peak device, input splitter and output combiner are integrated in a single
package. This package consists of one gate and drain lead and two extra leads of which
one is used for biasing the peak ampliï¬er and the other is not connected. It only requires
the proper input/output match and bias setting as with a normal class-AB transistor.
Table 1. Typical performance
RF performance at Th = 25 °C.
Mode of operation
f
(MHz)
TD-SCDMA [1][2]
2010 to 2025
VDS PL(AV)
(V) (W)
28 8
Gp ηD ACPR
(dB) (%) (dBc)
13.5 42 â23
[1] Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF.
[2] IDq = 170 mA (main); VGS(amp)peak = 0 V.
PL(3dB)
(W)
50
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
I Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz:
N Average output power = 8 W
N Power gain = 13.5 dB
N Efï¬ciency = 42 %
I Fully optimized integrated Doherty concept:
N integrated asymmetrical power splitter at input
N integrated power combiner
N peak biasing down to 0 V
N low junction temperature
N high efï¬ciency
I Integrated ESD protection
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