ADC1415S065 Datasheet, PDF(1/33 Page) NXP Semiconductors – Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs

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ADC1415S065 Datasheet, PDF (1/33 Pages) NXP Semiconductors – Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs

ADC1415S065/080/105/125

Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer

CMOS or LVDS DDR digital outputs

Rev. 02 â 4 June 2009

Objective data sheet

1. General description

The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1415S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

thanks to a separate digital output supply.

The ADC1415S supports the LVDS (Low Voltage Differential Signalling) DDR (Double

Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user

to easily conï¬gure the ADC.

The device also includes a programmable gain ampliï¬er with a ï¬exible input voltage

range. With excellent dynamic performance from the baseband to input frequencies of

170 MHz or more, the ADC1415S is ideal for use in communications, imaging and

medical applications - especially in high Intermediate Frequency (IF) applications thanks

to the integrated input buffer. The input buffer ensures that the input impedance remains

constant and low and the performance consistent over a wide frequency range.

2. Features

I SNR, 73 dB / SFDR, 90 dBc

I Input bandwidth, 600 MHz

I Pin compatible with the

I Power dissipation, 587 mW at 80 Msps,

ADC1410S065/080/105/125

including analog input buffer

I Sample rate up to 125 Msps

I SPI Interface

I 14-bit pipelined ADC core

I Duty cycle stabilizer

I Integrated input buffer

I Fast OTR detection

I Flexible input voltage range: 1 V (p-p) to I Offset binary, 2âs complement, gray

2 V (p-p) with 6 dB programmable

code

ï¬ne gain

I CMOS or LVDS DDR digital outputs I Power-down and Sleep modes

I INL Â±1 LSB, DNL Â±0.5 LSB (typical) I HVQFN40 package

3. Applications

I Wireless and wired broadband communications

I Spectral analysis

I Portable instrumentation

I Ultrasound equipment

I Imaging systems

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