ADC1213D_11 Datasheet, PDF (1/42 Pages) NXP Semiconductors – Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

ADC1213D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 6 — 9 February 2011
Product data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a programmable full-scale SPI to allow flexible input
voltage range of 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
 SNR, 70 dBFS; SFDR, 86 dBc
 Sample rate up to 125 Msps
 Clock input divided by 2 for less jitter
contribution
 3 V, 1.8 V single supplies
 Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
 Two configurable serial outputs
 Compliant with JESD204A serial
transmission standard
 Pin compatible with the
ADC1613D series, ADC1413D series,
and ADC1113D125
 Input bandwidth, 600 MHz
 Power dissipation, 995 mW at 80 Msps
 SPI register programming
 Duty cycle stabilizer (DCS)
 High IF capability
 Offset binary, two’s complement, gray
code
 Power-down mode and Sleep mode
 HVQFN56 package