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ADC1207S080 Datasheet, PDF (1/21 Pages) NXP Semiconductors – Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF
sampling
Rev. 02 — 7 August 2008
Product data sheet
1. General description
The ADC1207S080 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct
Input Frequency (IF) sampling and supporting the most demanding use conditions in ultra
high IF radio transceivers for cellular infrastructure and other applications such as wireless
infrastructure, optical networking and fixed telecommunication. Due to its broadband input
capabilities, the ADC1207S080 is ideal for single and multiple carriers data conversion.
Operating at a maximum sampling rate of 80 MHz, analog input signals are converted into
12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output
signals are Low-Voltage Complementary Metal-Oxide Semiconductor (LVCMOS)
compatible. The ADC1207S080 offers the most flexible acquisition control system
because of its programmable Complete Conversion Signal (CCS) that allows to adjust the
delay of the acquisition clock.
The ADC1207S080 offers the lowest input capacitance (< 1 pF) and therefore the highest
flexibility in front-end aliasing filter strategy because of its internal front-end buffer.
2. Features
I 12-bit resolution
I Differential input with 375 MHz bandwidth
I 90 dB SFDR; 71 dB S/N (fi = 225 MHz; fclk = 80 MHz; B = 5 MHz)
I 74 dB SFDR; 66.5 dB S/N (fi = 175 MHz; fclk = 80 MHz; B = Nyquist)
I High speed sampling rate up to 80 MHz
I Internal front-end buffer (input capacitance < 1 pF)
I Programmable acquisition output clock (complete conversion signal)
I Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale
I Single 5 V power supply
I 3.3 V LVCMOS compatible digital outputs
I Binary or two’s-complement LVCMOS outputs
I CMOS compatible static digital inputs
I Only 2 clock cycles latency
I Industrial temperature range from −40 °C to +85 °C
I HTQFP48 package