74LVT273 Datasheet, PDF (1/17 Pages) NXP Semiconductors – 3.3V Octal D flip-flop

74LVT273
3.3 V octal D-type flip-flop
Rev. 03 — 10 September 2008
Product data sheet
1. General description
The 74LVT273 is a high-performance BiCMOS product designed for V_CC operation at
3.3 V.
This device has eight edge-triggered D-type flip-flops with individual D inputs and Q
outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage
level on the MR input. The device is useful for applications where only the true output is
required and the CP and MR are common elements.
2. Features
I Eight edge-triggered D-type flip-flops
I Buffered common clock and asynchronous master reset
I Input and output interface capability to systems at 5 V supply
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Output capability: +64 mA/−32 mA
I Latch-up protection
N JESD78 Class II exceeds 500 mA
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
I Live insertion/extraction permitted
I Power-up reset
I No bus current loading when output is tied to 5 V bus