74LVC821ABQ Datasheet, PDF (1/20 Pages) List of Unclassifed Manufacturers – 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 4 — 23 November 2012
Product data sheet
1. General description
The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an
output enable input (pin OE) are common to all flip-flops. The ten flip-flops store the state
of their individual D-inputs that meet the set-up and hold times requirements on the
LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops are
available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE inputs does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
 5 V tolerant inputs and outputs; for interfacing with 5 V logic
 Wide supply voltage range from 1.2 V to 3.6 V
 CMOS low power consumption
 Direct interface with TTL levels
 Flow-through pinout architecture
 10-bit positive edge-triggered register
 Independent register and 3-state buffer operation
 Complies with JEDEC standard:
 JESD8-7A (1.65 V to 1.95 V)
 JESD8-5A (2.3 V to 2.7 V)
 JESD8-C/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-B exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Specified from 40 C to +85 C and 40 C to +125 C.