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74LVC3G17 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Triple non-inverting Schmitt trigger with 5 V tolerant input | |||
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74LVC3G17
Triple non-inverting Schmitt trigger with 5 V tolerant input
Rev. 06 â 6 June 2008
Product data sheet
1. General description
The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action. It is
capable of transforming slowly changing input signals into sharply deï¬ned, jitter-free
output signals.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully speciï¬ed for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backï¬ow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low-power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Multiple package options
I Speciï¬ed from â40 °C to +85 °C and â40 °C to +125 °C
3. Applications
I Wave and pulse shapers for highly noisy environments
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