74LVC2G17GW-G Datasheet, PDF(1/19 Page) NXP Semiconductors – Dual non-inverting Schmitt trigger with 5 V tolerant input

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74LVC2G17GW-G Datasheet, PDF (1/19 Pages) NXP Semiconductors – Dual non-inverting Schmitt trigger with 5 V tolerant input

74LVC2G17

Dual non-inverting Schmitt trigger with 5 V tolerant input

Rev. 8 â 2 May 2013

Product data sheet

1. General description

The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable

of transforming slowly changing input signals into sharply defined, jitter-free output

signals.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF.

The IOFF circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

ï® Wide supply voltage range from 1.65 V to 5.5 V

ï® 5 V tolerant input/output for interfacing with 5 V logic

ï® High noise immunity

ï® Complies with JEDEC standard:

ïµ JESD8-7 (1.65 V to 1.95 V)

ïµ JESD8-5 (2.3 V to 2.7 V)

ïµ JESD-8B/JESD36 (2.7 V to 3.6 V)

ï® ESD protection:

ïµ HBM JESD22-A114F exceeds 2000 V

ïµ MM JESD22-A115-A exceeds 200 V

ï® ï±24 mA output drive (VCC = 3.0 V)

ï® CMOS low-power consumption

ï® Latch-up performance exceeds 250 mA

ï® Direct interface with TTL levels

ï® Multiple package options

ï® Specified from ï40 ï°C to +85 ï°C and ï40 ï°C to +125 ï°C

3. Applications

ï® Wave and pulse shapers for highly noisy environments

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