74LVC2G14 Datasheet, PDF(1/17 Page) NXP Semiconductors – Dual inverting Schmitt-trigger with 5 V tolerant input

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74LVC2G14 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Dual inverting Schmitt-trigger with 5 V tolerant input

74LVC2G14

Dual inverting Schmitt trigger with 5 V tolerant input

Rev. 04 â 4 September 2007

Product data sheet

1. General description

The 74LVC2G14 provides two inverting buffers with Schmitt-trigger action.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the inputs

makes the circuit tolerant of slower input rise and fall time. This device is fully speciï¬ed for

partial power-down applications using IOFF. The IOFF circuitry disables the output,

preventing the damaging backï¬ow current through the device when it is powered down.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant inputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8B/JESD36 (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I Â±24 mA output drive (VCC = 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Unlimited rise and fall times

I Input accepts voltages up to 5 V

I Multiple package options

I Speciï¬ed from â40 Â°C to +85 Â°C and â40 Â°C to +125 Â°C.

3. Applications

I Wave and pulse shaper

I Astable multivibrator

I Monostable multivibrator

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