74LVC2G126_08 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Dual bus buffer/line driver; 3-state

74LVC2G126
Dual bus buffer/line driver; 3-state
Rev. 08 — 5 May 2008
Product data sheet
1. General description
The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each
3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE
causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all
inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G126 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (V_CC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C