74LVC1G79 Datasheet, PDF (1/16 Pages) NXP Semiconductors – Single D-type flip-flop; positive-edge trigger

74LVC1G79
Single D-type flip-flop; positive-edge trigger
Rev. 07 — 29 August 2007
Product data sheet
1. General description
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition
of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I_OFF. The I_OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8B/JESD36 (2.7 V to 3.6 V)
s ±24 mA output drive (V_CC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s ESD protection:
x HBM JESD22-A114E exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
s Specified from −40 °C to +125 °C