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74LVC1G57 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Low-power configurable multiple function gate | |||
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74LVC1G57
Low-power conï¬gurable multiple function gate
Rev. 03 â 19 July 2007
Product data sheet
1. General description
The 74LVC1G57 provides conï¬gurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully speciï¬ed for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backï¬ow current through
the device when it is powered down.
All inputs (A, B and C) have Schmitt trigger action. They are capable of transforming
slowly changing input signals into sharply deï¬ned, jitter-free output signals.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8B/JESD36 (2.7 V to 3.6 V)
s ±24 mA output drive (VCC = 3.0 V)
s ESD protection:
x HBM JESD22-A114E exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Speciï¬ed from â40 °C to +85 °C and â40 °C to +125 °C
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