74LVC1G10 Datasheet, PDF (1/14 Pages) NXP Semiconductors – Single 3-input NAND gate

74LVC1G10
Single 3-input NAND gate
Rev. 01 — 2 October 2007
Product data sheet
1. General description
The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
time.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V).
s ±24 mA output drive (V_CC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s ESD protection:
x HBM JESD22-A114E exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C