74HC4060-Q100 Datasheet, PDF (1/24 Pages) NXP Semiconductors – 14-stage binary ripple counter with oscillator

74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
Rev. 1 — 2 August 2012
Product data sheet
1. General description
The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC4060-Q100; 74HCT4060-Q100 are 14-stage ripple-carry counter/dividers and
oscillators with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to
Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator
configuration allows design of either RC or crystal oscillator circuits. The oscillator may be
replaced by an external clock signal at input RS. In this case keep the other oscillator pins
(RTC and CTC) floating. The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of
other input conditions. In the HCT version, the MR input is TTL compatible, but the RS
input has CMOS input switching levels and can be driven by a TTL output by using a
pull-up resistor to V_CC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 All active components on chip
 RC or crystal oscillator configuration
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
3. Applications
 Control counters
 Timers
 Frequency dividers
 Time-delay circuits