74HC257 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Quad 2-input multiplexer 3-state

74HC257; 74HCT257
Quad 2-input multiplexer; 3-state
Rev. 05 — 13 January 2010
Product data sheet
1. General description
The 74HC257; 74HCT257 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC257 and 74HCT257 have four identical 2-input multiplexers with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data
inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the
outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.
The 74HC257 and 74HCT257 are the logic implementation of a 4-pole, 2-position switch,
where the position of the switch is determined by the logic levels applied to S. The outputs
are forced to a high-impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
1Y = OE • (1I1 • S • 1I0 • S)
2Y = OE • (2I1 • S • 2I0 • S)
3Y = OE • (3I1 • S • 3I0 • S)
4Y = OE • (4I1 • S • 4I0 • S)
Except for their non-inverting (true) outputs the 74HC257; 74HCT257 are identical to the
74HC258.
2. Features
„ Non-inverting data path
„ 3-state outputs interface directly with system bus
„ Complies with JEDEC standard no. 7A
„ ESD protection:
‹ HBM JESD22-A114E exceeds 2000 V
‹ MM JESD22-A115-A exceeds 200 V
„ Multiple package options
„ Specified from −40 °C to +85 °C and from −40 °C to +125 °C