74CBTLV1G125 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Single bus switch

74CBTLV1G125
Single bus switch
Rev. 01 — 23 February 2007
Product data sheet
1. General description
The 74CBTLV1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled
when the output enable (OE) input is high.
To ensure the high-impedance OFF-state during power up or power down, OE should be
tied to the V_CC through a pullup resistor. The minimum value of the resistor is determined
by the current-sinking capability of the driver.
2. Features
s Supply voltage range from 2.3 V to 3.6 V
s High noise immunity
s Complies with JEDEC standard:
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-D exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s 5 Ω switch connection between two ports
s Rail to rail switching on data I/O ports
s CMOS low power consumption
s Latch-up performance meets requirements of JESD78 Class I
s I_OFF circuitry provides partial power down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C