74AVCH1T45 Datasheet, PDF (1/22 Pages) NXP Semiconductors – Dual supply translating transceiver; 3-state

74AVCH1T45
Dual supply translating transceiver; 3-state
Rev. 01 — 25 October 2007
Product data sheet
1. General description
The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (A and B), a direction control input (DIR)
and dual supply pins (V_CC(A) and V_CC(B)). Both V_CC(A) and V_CC(B) can be supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for translating between any of
the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are
referenced to V_CC(A) and pin B is referenced to V_CC(B). A HIGH on DIR allows transmission
from A to B and a LOW on DIR allows transmission from B to A.
The device is fully specified for partial power-down applications using I_OFF. The I_OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
s Wide supply voltage range:
x V_CC(A): 0.8 V to 3.6 V
x V_CC(B): 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114E Class 3B exceeds 8000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Maximum data rates:
x 500 Mbit/s (1.8 V to 3.3 V translation)
x 320 Mbit/s (< 1.8 V to 3.3 V translation)
x 320 Mbit/s (translate to 2.5 V or 1.8 V)
x 280 Mbit/s (translate to 1.5 V)