74AVC2T45_09 Datasheet, PDF (1/32 Pages) NXP Semiconductors – Dual-bit, dual-supply voltage level translator/transceiver; 3-state

74AVC2T45
Dual-bit, dual-supply voltage level translator/transceiver;
3-state
Rev. 04 — 5 May 2009
Product data sheet
1. General description
The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level
translation. It features two data input-output ports (nA and nB), a direction control input
(DIR) and dual-supply pins (V_CC(A) and V_CC(B)). Both V_CC(A) and V_CC(B) can be supplied at
any voltage between 0.8 V and 3.6 V making the device suitable for translating between
any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR
are referenced to V_CC(A) and pins nB are referenced to V_CC(B). A HIGH on DIR allows
transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The device is fully specified for partial power-down applications using I_OFF. The I_OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In Suspend mode when either V_CC(A) or V_CC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
2. Features
I Wide supply voltage range:
N V_CC(A): 0.8 V to 3.6 V
N V_CC(B): 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 500 Mbit/s (1.8 V to 3.3 V translation)
N 320 Mbit/s (< 1.8 V to 3.3 V translation)
N 320 Mbit/s (translate to 2.5 V or 1.8 V)
N 280 Mbit/s (translate to 1.5 V)
N 240 Mbit/s (translate to 1.2 V)
I Suspend mode
I Latch-up performance exceeds 100 mA per JESD 78 Class II