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74AUP2G17_09 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Low-power dual Schmitt trigger | |||
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74AUP2G17
Low-power dual Schmitt trigger
Rev. 03 â 6 July 2009
Product data sheet
1. General description
The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly
changing input signals into sharply deï¬ned, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully speciï¬ed for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backï¬ow current through
the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VTâ is deï¬ned as the input
hysteresis voltage VH.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Speciï¬ed from â40 °C to +85 °C and â40 °C to +125 °C
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