74AUP2G157 Datasheet, PDF (1/20 Pages) NXP Semiconductors – Low-power 2-input multiplexer

74AUP2G157
Low-power 2-input multiplexer
Rev. 03 — 2 July 2008
Product data sheet
1. General description
The 74AUP2G157 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs
(I0 and I1) under control of a common data select input (S). The state of the common data
select input determines the particular register from which the data comes. The output
(Y, Y) presents the selected data in the true (non-inverted) and complement form. The
enable input (E) is active LOW. When E is HIGH, the output Y is forced LOW and the
output Y is forced HIGH regardless of all other input conditions.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; I_CC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of V_CC
I I_OFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C