74AUP2G14 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Low-power dual Schmitt trigger inverter

74AUP2G14
Low-power dual Schmitt trigger inverter
Rev. 02 — 3 July 2009
Product data sheet
1. General description
The 74AUP2G14 provides two inverting buffers with Schmitt trigger action which accept
standard input signals. They are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I_OFF. The I_OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V_T+ and the negative voltage V_T− is defined as the input
hysteresis voltage V_H.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; I_CC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of V_CC
I I_OFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
I Wave and pulse shaper
I Astable multivibrator
I Monostable multivibrator