74AUP1T58 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Low-power configurable gate with voltage-level translator

74AUP1T58
Low-power configurable gate with voltage-level translator
Rev. 02 — 29 September 2009
Product data sheet
1. General description
The 74AUP1T58 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to
V_CC or GND.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 2.3 V to 3.6 V.
The 74AUP1T58 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V_CC range.
2. Features
I Wide supply voltage range from 2.3 V to 3.6 V
I High noise immunity
I ESD protection:
N HBM JESD22-A114F Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; I_CC = 1.5 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78B Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of V_CC
I I_OFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C