74AUP1T34 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Low-power dual supply translating buffer

74AUP1T34
Low-power dual supply translating buffer
Rev. 01 — 4 December 2006
Product data sheet
1. General description
The 74AUP1T34 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 1.1 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire V_CC range from 1.1 V to 3.6 V.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is
designed to track V_CC(A). Output Y is designed to track V_CC(Y). Both, V_CC(A) and V_CC(Y)
accepts any supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage
interfacing between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
2. Features
s Wide supply voltage range from 1.1 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-D Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Wide supply voltage range:
x V_CC(A): 1.1 V to 3.6 V
x V_CC(Y): 1.1 V to 3.6 V
s Low static power consumption; I_CC = 0.9 µA (maximum)
s Each port operates over the full 1.1 V to 3.6 V power supply range
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of V_CC
s I_OFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C