74AUP1G374 Datasheet, PDF (1/20 Pages) NXP Semiconductors – Low-power D-type flip-flop; positive-edge trigger; 3-state

74AUP1G374
Low-power D-type flip-flop; positive-edge trigger; 3-state
Rev. 04 — 26 June 2009
Product data sheet
1. General description
The 74AUP1G374 provides the single D-type flip-flop with 3-state output. The flip-flop will
store the state of data input (D) that meet the set-up and hold times requirements on the
LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the flip-flop is available
at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance
OFF-state. Operation of input pin OE does not affect the state of the flip-flop.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; I_CC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of V_CC
I I_OFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C