74AUP1G34-Q100 Datasheet, PDF (1/14 Pages) NXP Semiconductors – Low-power buffer

74AUP1G34-Q100
Low-power buffer
Rev. 1 — 26 March 2013
Product data sheet
1. General description
The 74AUP1G34-Q100 provides a low-power, low-voltage single buffer.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V_CC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V_CC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I_OFF.
The I_OFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
 HBM JESD22-A114F Class 3A. Exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Low static power consumption; I_CC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of V_CC
 I_OFF circuitry provides partial power-down mode operation
 Multiple package options