74AHCT02D Datasheet, PDF (1/14 Pages) NXP Semiconductors – Quad 2-input NOR gate

74AHC02; 74AHCT02
Quad 2-input NOR gate
Rev. 04 — 21 May 2008
Product data sheet
1. General description
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accept voltages higher than V_CC
I Input levels:
N For 74AHC02: CMOS level
N For 74AHCT02: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74AHC02
74AHC02D
−40 °C to +125 °C SO14
74AHC02PW −40 °C to +125 °C TSSOP14
74AHC02BQ
−40 °C to +125 °C DHVQFN14
Description
Version
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm