74AHC574 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Octal D-type flip-flop; positive edge-trigger; 3-state

74AHC574; 74AHCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 02 — 24 January 2008
Product data sheet
1. General description
The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but
has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to
the 74AHC374; 74AHCT374, but has a different pinning.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I 3-state non-inverting outputs for bus orientated applications
I 8-bit positive, edge-triggered register
I Independent register and 3-state buffer operation
I Common 3-state output enable input
I For 74AHC574 only: operates with CMOS input levels
I For 74AHCT574 only: operates with TTL input levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C