74AHC30_09 Datasheet, PDF (1/14 Pages) NXP Semiconductors – 8-input NAND gate

74AHC30; 74AHCT30
8-input NAND gate
Rev. 03 — 26 June 2009
Product data sheet
1. General description
The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC30; 74AHCT30 provides an 8-input NAND function.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than V_CC
I Input levels:
N For 74AHC30: CMOS level
N For 74AHCT30: TTL level
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74AHC30D
−40 °C to +125 °C SO14
74AHCT30D
74AHC30PW −40 °C to +125 °C TSSOP14
74AHCT30PW
74AHC30BQ
−40 °C to +125 °C DHVQFN14
74AHCT30BQ
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm