74AHC273_08 Datasheet, PDF (1/18 Pages) NXP Semiconductors – Octal D-type flip-flop with reset; positive-edge trigger

74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 03 — 13 May 2008
Product data sheet
1. General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D
inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops
simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than V_CC
I Ideal buffer for MOS microcontroller or memory
I Common clock and master reset
I Related product versions:
N 74AHC377; 74AHCT377 for clock enable version
N 74AHC373; 74AHCT373 for transparent latch version
N 74AHC374; 74AHCT374 for 3-state version
I Input levels:
N For 74AHC273: CMOS level
N For 74AHCT273: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C