74AHC259_08 Datasheet, PDF (1/17 Pages) NXP Semiconductors – 8-bit addressable latch

74AHC259; 74AHCT259
8-bit addressable latch
Rev. 02 — 15 May 2008
Product data sheet
1. General description
The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC259; 74AHCT259 is a high-speed 8-bit addressable latch designed for general
purpose storage applications in digital systems. It is a multifunctional device capable of
storing single-line data in eight addressable latches and providing a 3-to-8 decoder and
multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates an active
LOW common reset (MR) for resetting all latches as well as an active LOW enable input
(LE).
The 74AHC259; 74AHCT259 has four modes of operation:
• In the addressable latch mode, data on the data line (D) is written into the addressed
latch. The addressed latch will follow the data input with all non-addressed latches
remaining in their previous states.
• In the memory mode, all latches remain in their previous states and are unaffected by
the data or address inputs.
• In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state
of the data input (D) with all other outputs in the LOW state.
• In the reset mode, all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74AHC259; 74AHCT259 as an address latch, changing more than
one bit of the address could impose a transient-wrong address. Therefore, this should
only be done while in the memory mode.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Combines demultiplexer and 8-bit latch
I Serial-to-parallel capability
I Output from each storage bit available
I Random (addressable) data entry
I Easily expandable
I Common reset input
I Useful as a 3-to-8 active HIGH decoder
I Inputs accept voltages higher than V_CC