74AHC02 Datasheet, PDF (1/13 Pages) NXP Semiconductors – Quad 2-input NOR gate

74AHC02; 74AHCT02
Quad 2-input NOR gate
Rev. 03 — 7 January 2008
Product data sheet
1. General description
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74AHC02; 74AHCT02 provides the quad 2-input NOR function.
2. Features
s Balanced propagation delays
s All inputs have a Schmitt-trigger action
s Inputs accepts voltages higher than V_CC
s For 74AHC02 only: operates with CMOS input levels
s For 74AHCT02 only: operates with TTL input levels
s ESD protection:
x HBM JESD22-A114E exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Multiple package options
s Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74AHC02D
74AHCT02D
−40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74AHC02PW
74AHCT02PW
−40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74AHC02BQ
74AHCT02BQ
−40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1