M25P40 Datasheet, PDF(32/53 Page) STMicroelectronics – 4 Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface

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M25P40 Datasheet, PDF (32/53 Pages) STMicroelectronics – 4 Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface

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Instructions

M25P40

6.11

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the Deep Power-down mode). It can also be used as an extra

software protection mechanism, while the device is not in active use, since in this mode, the

device ignores all Write, Program and Erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power

mode (if there is no internal cycle currently in progress). But this mode is not the Deep

Power-down mode. The Deep Power-down mode can only be entered by executing the

Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to

ICC2, as specified in Table 13).

Once the device has entered the Deep Power-down mode, all instructions are ignored

except the Release from Deep Power-down and Read Electronic Signature (RES)

instruction. This releases the device from this mode. The Release from Deep Power-down

and Read Electronic Signature (RES) instruction and the Read Identification (RDID)

instruction also allow the Electronic Signature of the device to be output on Serial Data

output (Q).

The Deep Power-down mode automatically stops at Power-down, and the device always

Powers-up in the Standby Power mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced

to ICC2 and the Deep Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Deep Power-down (DP) instruction sequence

01234567

tDP

Instruction

Stand-by Mode Deep Power-down Mode

AI03753D

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