M29W128FH Datasheet, PDF (16/78 Pages) Numonyx B.V – 128 Mbit (8Mb x 16 or 16Mb x 8, Page, Uniform Block) 3V Supply Flash Memory

Bus operations
3
Bus operations
M29W128FH, M29W128FL
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
See Table 2 and Table 5, Bus Operations, for a summary. Typically glitches of less than 5ns
on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by
the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words (or
16 Bytes) and is addressed by the address inputs A2-A0 in x16 mode and A2-DQ15A−1 in
Byte mode.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, V_IL, to Chip Enable and Output Enable and keeping Write Enable
High, V_IH. The Data Inputs/Outputs will output the value, see Figure 9: Random Read AC
waveforms, Figure 10: Page Read AC waveforms (Word mode), and Table 21: Read AC
characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V_IH,
during the whole Bus Write operation. See Figure 11 and Figure 12, Write AC Waveforms,
and Table 22 and Table 23, Write AC Characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V_IH.
3.4
Standby
When Chip Enable is High, V_IH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I_CC2, Chip Enable should be held within V_CC ± 0.3V. For the
Standby current level see Table 20: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I_CC3, for Program or Erase operations until the operation completes.
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