NAND08GW3C2A Datasheet, PDF (13/58 Pages) Numonyx B.V – 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory

NAND08GW3C2A, NAND16GW3C2A
2
Memory array organization
Memory array organization
The memory array is comprised of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 128 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data, whereas the spare area is typically used to store software flags or bad block
identification.
The pages are split into a 2048-byte main area and a spare area of 64 bytes. Refer to
Figure 6: Memory array organization.
2.1
Bad blocks
The NAND08GW3C2A and NAND16GW3C2A devices may contain bad blocks, where the
reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block Information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 3: Valid blocks shows the minimum number of valid blocks in each device. The values
shown include both the bad blocks that are present when the device is shipped and the bad
blocks that could develop later on.
These blocks need to be managed using Bad Blocks Management and Block Replacement
(refer to Section 9: Software algorithms).
Table 3. Valid blocks⁽¹⁾
Density of device
Minimum
Maximum
8 Gbits
16 Gbits
4016
8032
4096
8192
1. The NAND16GW3C4A is composed of two 8-Gbit dice. The minimum number of valid blocks is 4096 for
each die.
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