M24512-DFMC6TG Datasheet, PDF (13/47 Pages) Numonyx B.V – 128-Mbit, low-voltage, serial flash memory with 54-MHz SPI bus interface

M25P128
Operating features
4.5
Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to I_CC1.
4.6
Status register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.4: Read status register (RDSR) for a
detailed description of the Status Register bits.
4.7
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P128 features the following data protection mechanisms:
„ Power On Reset and an internal timer (t_PUW) can provide protection against
inadvertent changes while the power supply is outside the operating specification.
„ Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
„ All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
„ The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
„ The Write Protect (W/V_PP) signal allows the Block Protect (BP2, BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
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