NTE2732A Datasheet, PDF(3/6 Page) NTE Electronics – Integrated Circuit 32K (4K x 8) NMOS UV Erasable PROM

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NTE2732A Datasheet, PDF (3/6 Pages) NTE Electronics – Integrated Circuit 32K (4K x 8) NMOS UV Erasable PROM

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AC Waveforms:

ADDRESSES

OUTPUT

ADDRESSES VALID

tCE

HIGH Z

tACC

tDE (Note 6)

tDE (Note 7)

tOH

VALID OUTPUT

HIGH Z

Note 6. OE may be delayed up to tACC â tOE after the falling edge CE without impact on tACC.

Note 7. tDF is specified from OE or CE whichever occurs first.

Read Mode:

The NTE2732A has two control functions, both of which must be logically satisfied in order to obtain

data at the outputs. Chip Enable (CE) is the power control and should be used for device selection.

Output Enable (OE) is the output control and should be used to gate data to the output pins, indepen-

dent of device selection.

Assuming that addresses are stable, address access time (tACC) is equal to delay from CE to output

(tCE). Data is available at the outputs after the falling edge of OE, assuming that CE has been low

and addresses have been stable for at least tACCâtOE.

Standby Mode:

The NTE2732A has a standby mode which reduces the active power current by 70%, from 125mA

to 35mA. The NTE2732A is placed in the standby mode by applying a TTL high signal to CE input.

When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output ORâTieing:

Because NTE2732Aâs are usually used in larger memory arrays, the product features a 2 line control

function which accommodates the use of multiple memory connection. The two line control function

allows:

a) the lowest possible memory power dissipation

b) complete assurance that output bus contention will not occur

To most efficiently use these two control lines, it is recommended that CE be decoded and used as

the primary device selecting function, while OE should be made a common connection to all devices

in the array and connected to the READ line from the system control bus.

This assures that all deselected memory devices are in their low power standby mode and that the

output pins are only active when data is desired from a particular memory device.

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