DP83849ID Datasheet, PDF (95/98 Pages) National Semiconductor (TI) – PHYTER DUAL Industrial Temperature with Fiber Support (FX) Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

8.2.27 RMII Receive Timing
PMD Input Pair IDLE (J/K)
Data
T2.27.5
(TR)
Data
T2.27.4
X1
T2.27.3
RX_DV
CRS_DV
RXD[1:0]
RX_ER
T2.27.2
T2.27.1
T2.27.2
T2.27.2
T2.27.2
Parameter
Description
Notes
T2.27.1
X1 Clock Period
50 MHz Reference Clock
T2.27.2
RXD[1:0], CRS_DV, RX_DV
and RX_ER output delay from
X1 rising
T2.27.3
CRS ON delay (100Mb)
100BASE-TX mode
100BASE-FX mode
T2.27.4
CRS OFF delay (100Mb)
100BASE-TX mode
100BASE-FX mode
T2.27.5
RXD[1:0] and RX_ER latency 100BASE-TX mode
(100Mb)
100BASE-FX mode
Min Typ Max Units
20
ns
2
14 ns
18.5
bits
9
27
bits
17
38
bits
27
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may
toggle synchronously at the end of the packet to indicate CRS deassertion.
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of
receive data.
Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to initial assertion of
CRS_DV.
Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to initial deassertion of
CRS_DV.
Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with
the Elasticity Buffer set to the default value (01).
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