SM72442 Datasheet, PDF (9/14 Pages) National Semiconductor (TI) – Programmable Maximum Power Point Tracking Controller for Photovoltaic Solar Panels

RESET PIN
When the reset pin is pulled low, the chip will cease its normal
operation and turn-off all of its PWM outputs including the
output of PM_OUT pin. Below is an oscilloscope capture of a
forced reset condition.
specially important when sampling dynamic signals. Also im-
portant when sampling dynamic signals is a band-pass or low-
pass filter which reduces harmonic and noise in the input.
These filters are often referred to as anti-aliasing filters.
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FIGURE 9. Equivalent Input Circuit
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FIGURE 8. Forced Reset Condition
As seen in Figure 8, the initial value for output voltage and
load current are 28V and 1A respectively. After the reset pin
is grounded both the output voltage and load current de-
creases immediately. MOSFET switching on the buck-boost
converter also stops immediately. VLOB indicates the low
side boost output from the SM72295.
ANALOG INPUT
An equivalent circuit for one of the ADC input channels is
shown in Figure 9. Diode D1 and D2 provide ESD protection
for the analog inputs. The operating range for the analog in-
puts is 0V to V_A. Going beyond this range will cause the ESD
diodes to conduct and result in erratic operation.
The capacitor C1 in Figure 9 has a typical value of 3 pF and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch; it is typ-
ically 500Ω. Capacitor C2 is the ADC sampling capacitor; it is
typically 30 pF. The ADC will deliver best performance when
driven by a low-impedance source (less than 100Ω). This is
DIGITAL INPUTS and OUTPUTS
The digital input signals have an operating range of 0V to
V_A, where V_A = VDDA – VSSA. They are not prone to latch-
up and may be asserted before the digital supply V_D, where
V_D = VDDD – VSSD, without any risk. The digital output sig-
nals operating range is controlled by V_D. The output high
voltage is V_D – 0.5V (min) while the output low voltage is 0.4V
(max).
SDA and SCL OPEN DRAIN OUTPUT
SCL and SDA output is an open-drain output and does not
have internal pull-ups. A “high” level will not be observed on
this pin until pull-up current is provided by some external
source, typically a pull-up resistor. Choice of resistor value
depends on many system factors; load capacitance, trace
length, etc. A typical value of pull- up resistor for SM72442
ranges from 2 kΩ to 10 kΩ. For more information, refer to the
I2C Bus specification for selecting the pull-up resistor value .
The SCL and SDA outputs can operate while being pulled up
to 5V and 3.3V.
I2C CONFIGURATION REGISTERS
The operation of the SM72442 can be configured through its
I2C interface. Complete register settings for I2C lines are
shown below.
reg0 Register Description
Bits
Field
55:40
RSVD
39:30
ADC6
29:20
ADC4
19:10
ADC2
9:0
ADC0
Reset Value
16'h0
10'h0
10'h0
10'h0
10'h0
R/W
Bit Field Description
R
Reserved for future use.
R
Analog Channel 6 (slew rate detection time constant,
see adc config worksheet)
R
Analog Channel 4 (iout_max: maximum allowed output
current)
R
Analog Channel 2 (operating mode, see adc_config
worksheet)
R
Analog Channel 0 (vout_max: maximum allowed
output voltage)
reg1 Register Description
Bits
Field
Reset Value
R/W
55:43
RSVD
13'h0
R
42
burnin_n
1'h0
R
Bit Field Description
Reserved for future use.
over temperature input to IC
9
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