LMZ10503EXT Datasheet, PDF (9/22 Pages) National Semiconductor (TI) – 3A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage for Military and Rugged Applications

A second criteria before finalizing the C_in bypass capacitor is
the RMS current capability. The necessary RMS current rat-
ing of the input capacitor to a buck regulator can be estimated
by
R_ESR is the total output capacitor ESR, L is the inductance
value of the internal power inductor, where L = 2.2 µH, and
f_SW = 1 MHz. Therefore, per the design example:
With this high AC current present in the input capacitor, the
RMS current rating becomes an important parameter. The
maximum input capacitor ripple voltage and RMS current oc-
cur at 50% duty cycle. Select an input capacitor rated for at
least the maximum calculated I_Cin(RMS).
Additional bulk capacitance with higher ESR may be required
to damp any resonance effects of the input capacitance and
parasitic inductance.
Output Capacitor Selection
In general, 22 µF to 100 µF high quality dielectric (X5R, X7R)
ceramic capacitor rated at twice the maximum output voltage
is sufficient given the optimal high frequency characteristics
and low ESR of ceramic dielectrics. Although, the output ca-
pacitor can also be of electrolytic chemistry for increased
capacitance density.
Two output capacitance equations are required to determine
the minimum output capacitance. One equation determines
the output capacitance (C_O) based on PWM ripple voltage.
The second equation determines C_O based on the load tran-
sient characteristics. Select the largest capacitance value of
the two.
The minimum capacitance, given the maximum output volt-
age ripple (ΔV_OUT) requirement, is determined by the follow-
ing equation:
Where the peak to peak inductor current ripple (Δi_L) is equal
to:
The minimum output capacitance requirement due to the
PWM ripple voltage is:
Three miliohms is a typical R_ESR value for ceramic capacitors.
The following equation provides a good first pass capacitance
requirement for a load transient:
Where I_step is the peak to peak load step (for this example
I_step = 10% to 90% of the maximum load), V_FB = 0.8V, and
ΔV_{o_tran} is the maximum output voltage deviation, which is
±20 mV.
Therefore the capacitance requirement for the given design
parameters is:
C_o ≥ 42 µF
In this particular design the output capacitance is determined
by the load transient requirements.
Table 1 lists some examples of commercially available ca-
pacitors that can be used with the LMZ10503EXT.
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