LM5069_08 Datasheet, PDF (9/22 Pages) National Semiconductor (TI) – Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting

FIGURE 1. Basic Application Circuit
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Functional Description
The LM5069 is designed to control the in-rush current to the
load upon insertion of a circuit card into a live backplane or
other "hot" power source, thereby limiting the voltage sag on
the backplane’s supply voltage, and the dV/dt of the voltage
applied to the load. Effects on other circuits in the system are
minimized, preventing possible unintended resets. A con-
trolled shutdown when the circuit card is removed can also be
implemented using the LM5069. In addition to a pro-
grammable current limit, the LM5069 monitors and limits the
maximum power dissipation in the series pass device to main-
tain operation within the device Safe Operating Area (SOA).
Either current limiting or power limiting for an extended period
of time results in the shutdown of the series pass device. In
this event, the LM5069-1 latches off until the circuit is re-en-
abled by external control, while the LM5069-2 automatically
restarts with defined timing. The circuit breaker function
quickly switches off the series pass device upon detection of
a severe over-current condition. The Power Good (PGD) out-
put pin indicates when the output voltage is within 1.25V of
the system input voltage (V_SYS). Programmable under-volt-
age lock-out (UVLO) and over-voltage lock-out (OVLO) cir-
cuits shut down the LM5069 when the system input voltage
is outside the desired operating range. The typical configura-
tion of a circuit card with LM5069 hot swap protection is shown
in Figure 2.
FIGURE 2. LM5069 Application
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Power Up Sequence
The VIN operating range of the LM5069 is +9V to +80V, with
a transient capability to +100V. Referring to the Block Dia-
gram and Figure 1 and Figure 3, as the voltage at VIN initially
increases, the external N-channel MOSFET (Q1) is held off
by an internal 230 mA pull-down current at the GATE pin. The
strong pull-down current at the GATE pin prevents an inad-
vertent turn-on as the MOSFET’s gate-to-drain (Miller) ca-
pacitance is charged. Additionally, the TIMER pin is initially
held at ground. When the VIN voltage reaches the POR_IT
threshold (7.6V) the insertion time begins. During the inser-
tion time, the capacitor at the TIMER pin (C_T) is charged by a
5.5 µA current source, and Q1 is held off by a 2 mA pull-down
current at the GATE pin regardless of the VIN voltage. The
insertion time delay allows ringing and transients at VIN to
settle before Q1 can be enabled. The insertion time ends
when the TIMER pin voltage reaches 4.0V. C_T is then quickly
discharged by an internal 1.5 mA pull-down current. After the
insertion time, the LM5069 control circuitry is enabled when
VIN reaches the POR_EN threshold (8.4V). The GATE pin then
switches on Q1 when V_SYS exceeds the UVLO threshold (UV-
LO pin >2.5V). If V_SYS is above the UVLO threshold at the end
of the insertion time, Q1 switches on at that time. The GATE
pin charge pump sources 16 µA to charge Q1’s gate capaci-
tance. The maximum gate-to-source voltage of Q1 is limited
by an internal 12V zener diode.
As the voltage at the OUT pin increases, the LM5069 monitors
the drain current and power dissipation of MOSFET Q1. In-
rush current limiting and/or power limiting circuits actively
control the current delivered to the load. During the in-rush
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