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LM3407_09 Datasheet, PDF (9/16 Pages) National Semiconductor (TI) – 350 mA, Constant Current Output Floating Buck Switching Converter for High Power LEDs
FIGURE 2. LM3407 Switching Waveforms
The switching frequency and duty ratio of the converter equal:
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By comparing the area of VISNS and VRP over the ON period,
an error signal is generated. Such a comparison is function-
ally equivalent to comparing the middle level of ISNS to VRP
during the ON-period of a switching cycle. The error signal is
fed to a PWM comparator circuit to produce the PWM control
pulse to drive the internal power N-MOSFET. Figure 3 shows
the implementation of the PWM switching signal. The error
signal is fed to a PWM comparator circuit to produce the PWM
control pulse to drive the internal power N-MOSFET. Figure
3 shows the implementation of the PWM switching signal.
In closed loop operation, the difference between VMSL and
VRP is reflected in the changes of the switching duty cycle of
the power switch. This behavior is independent of the induc-
tance of the inductor and input voltage because for the same
set of IOUT * RISNS, ON time, and switching period, there exists
only one VMSL. Figure 4 shows two sets of current sense sig-
nals named VISNS1 and VISNS2 that have identical frequencies
and duty cycles but different shapes of trapezoidal wave-
forms, each generating identical PWM signals.
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FIGURE 3. Pulse-Level Transformation
When VMSL is higher than VREF, the peak value of VRP, the
switching duty cycle of the power switch will be reduced to
lower VMSL. When VMSL is lower than the peak value of VRP,
the switching duty cycle of the power switch will be increased
to raise VMSL. For example, when IOUT is decreased, VMSL will
become lower than VREF. In order to maintain output current
regulation, the switching duty cycle of the power switch will
be increased and eventually push up VMSL until VMSL equals
VREF. Since in typical floating buck regulators VMSL is equal
to IOUT * RISNS, true average output current regulation can be
achieved by regulating VMSL. Figure 5 shows the waveforms
of VISNS and VRP under closed loop operation.
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