DS90C383B Datasheet, PDF (9/11 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

Applications Information
The DS90C383B are backward compatible with the
DS90C383/DS90CF383, DS90C383A/DS90CF383A and
are a pin-for-pin replacement.
This device may also be used as a replacement for the
DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
the V_CC, LVDS V_CC and PLL V_CC of the transmitter.
2. The DS90C383B transmitter input and control inputs
accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
3. To implement a falling edge device for the DS90C383B,
the R_FB pin (pin 17) may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVC-
MOS and LVTTL levels. These pins are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
The DS90C383B does not require any special requirement
for sequencing of the input clock/data and PD (PowerDown)
signal. The DS90C383B offers a more robust input sequenc-
ing feature where the input clock/data can be inserted after
the release of the PD signal. In the case where the clock/
data is stopped and reapplied, such as changing video mode
within Graphics Controller, it is not necessary to cycle the PD
signal. Asserting the PWR DOWN pin will effectively place
the device in reset and disable the PLL, enabling the LVDS
Transmitter into a power saving standby mode. However, it is
still generally a good practice to assert the PWR DOWN pin
or reset the LVDS transmitter whenever the clock/data is
stopped and reapplied but it is not mandatory for the
DS90C383B.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C383B can support Spread Spectrum Clocking
signal type inputs. The DS90C383B outputs will accurately
track Spread Spectrum Clock/Data inputs with modulation
frequencies of up to 100kHz (max.)with either center spread
of ±2.5% or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have V_CC, LVDS
V_CC and PLL V_CC from the same power source with three
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
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