DS90C383A Datasheet, PDF (9/11 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

8.0 DS90CF383A Pin Description — FPD Link Transmitter (Continued)
Pin Name
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
I
4
I
1
I
2
I
1
I
3
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Description
9.0 Applications Information
The DS90C383A/DS90CF383A are backward compatible
with the DS90C383/DS90CF383 and are a pin-for-pin re-
placement. The device (DS90C383A/DS90CF383A) utilizes
a different PLL architecture employing an internal 7X clock
for enhanced pulse position control.
This device (DS90C383A/DS90CF383A) also features re-
duced variation of the TCCD parameter which is important
for dual pixel applications. (See AN-1084) TCCD variation
has been measured to be less than 250ps at 65MHz under
normal operating conditions.
This device may also be used as a replacement for the
DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
the V_CC, LVDS V_CC and PLL V_CC of the transmitter.
2. The DS90C383A transmitter input and control inputs ac-
cept 3.3V TTL/CMOS levels. They are not 5V tolerant.
3. To implement a falling edge device for the DS90C383A,
the R_FB pin (pin 17) may be tied to ground OR left un-
connected (an internal pull-down resistor biases this pin
low). Biasing this pin to Vcc implements a rising edge
device.
10.0 Transmitter Clock Jitter Cycle-to-Cycle
Figures 12 and 13 illustrate the timing of the input clock rela-
tive to the input data. The input clock (TxCLKin) is intention-
ally shifted to the left −3ns and +3ns to the right when data
(Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter is re-
peated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-to-
cycle jitter at 2µs period.
9
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